1. Field of the Invention
This invention relates to the field of testers for integrated circuits. More specifically, the invention relates to a device to hold and align an integrated circuit within a tester.
2. Description of the Related Art
A chip is the smallest unit of fabrication in semiconductor technologies. A single chip normally contains multiple transistors that are connected into more useful entities known as logic gates. Complex chips have many logic gates, forming multiple logic circuits. Very Large Scale Integrated (VLSI) circuit chips, a class of chips with very dense circuitry, can host millions of transistors per chip, and can embody a number of computational devices on a single chip, including memories and microprocessors.
As presently fabricated, a chip is a thin (0.2 to 0.25 mm) piece of square or rectangular silicon encapsulated in an outer package. This package (for example, a dual inline package (DIP), a ball grid array package, a leadless carrier, or the like) provides pins that electrically connect the chip to its operating environment, normally a printed circuit board. The silicon chips are generally first fabricated as a matrix of dozens or even hundreds of dies that are etched on a large slice of silicon, termed a wafer. After fabrication, the wafer is diced and the individual dies are packaged into chips. Each die, while still on the wafer, includes electrical contacts that allow electrical signals to be input and output from the die circuitry.
VLSI chips must be tested both during the prototype stages of development and thereafter during mass production, to first verify the integrity of their design, and then to verify the quality of their manufacture. Testing can be performed either prior to or after packaging. Design verification systems have been developed that selectively excite the inputs of an integrated circuit chip with many input combinations, called test vectors. The outputs of the chip in response to the test vectors are checked for accuracy. For every test vector, there is an expected output, which is defined by the function performed by the electronic circuitry located within the chip. If there is a discrepancy between the expected output and the actual output when the circuit is presented with a specific test vector, there is likely a design error or, later, a manufacturing error in the chip. By testing a large number of input combinations, the likelihood that a design or manufacturing fault in the chip will pass undetected is significantly reduced, if not eliminated.
A typical design verifier used to test prototype chips includes a metallic chassis that holds the electronic circuitry necessary to test a chip, termed the device-under-test (DUT). The circuitry undergoing testing is typically mounted on a printed circuit board that electromechanically positions the integrated circuit device such that the pins of the chip can be connected to the test circuitry in the chassis. This circuit board, generally known as a DUT board, also functions to maintain a controlled impedance signal path from the test electronics to the chip pins. This is normally accomplished by providing paths of near equal length for electrical signal travel. The DUT board is also normally removable, so that removable connecting wires can be easily placed between the chip pins in the center of the board and the input/output (I/O) stimulus connections on the periphery of the board.
To ensure proper operation of a chip under a variety of conditions, tests are performed using a wide range of operating parameters. For example, the chip may be tested for over a wide temperature range. This change in temperature may cause thermal expansion or contraction of the device holding the chip on the tester. Further, operation of the chip itself generates heat, and this heat may also contribute to the thermal expansion of the device.
A typical design verifier holds a large number of chips in close proximity to one another. Because of slight changes in the relative positions of the connections between the DUT board and the test system, signal integrity with the DUT may be lost. Such differences may be caused by thermal expansion and retraction, machining tolerances, physical movement, or other factors. A system is needed that permits some variation between the DUT board and the test system with sacrificing signal integrity.